This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-269423, filed Sep. 5, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory, such as a flash memory, and more particularly to an address allocating method for a nonvolatile semiconductor memory with a page mode (page reading function).
2. Description of the Related Art
One known nonvolatile semiconductor memory is a flash memory. FIG. 1 is a sectional view of a memory cell in the flash memory. The memory cell (or memory cell transistor) is composed of a MOSFET (Metal Oxide Semiconductor Field-Effect Transistor), which has a stacked-gate structure where a floating gate FG and a control gate CG are stacked on top of the other via an insulating film. Specifically, in this example, an N-well region 101 is formed in a P-substrate. In the N-well region 101, a P-well region 102 is formed. At the surface of the P-well region 102, an n+-type impurity diffused region 103 acting as the drain region of the MOSFET, an n+-type impurity diffused region 104 acting as the source region, and a p+-type impurity diffused region 105 are formed. On the substrate 100 between the impurity diffused regions 103 and 104, a gate insulating film 106, a floating gate FG, an insulating film 107, and a control gate CG are stacked in that order. At the surface of the N-well region 101, there is provided an n+-type impurity diffused region 108, which is connected to the impurity diffused region 104 and impurity diffused region 105. In addition, at the main surface of the substrate 100, there is provided a p+-type impurity diffused region 109, which is then connected to the ground point.
In the memory cell transistor, the threshold voltage with respect to the control gate CG changes (or shifts) according to the number of electrons accumulated in the floating gate FG. The memory cell transistor stores xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d data according to a change in the threshold voltage.
FIG. 2 shows a part of a memory cell array where units of the memory cell transistor are arranged in a matrix. The control gates of the individual memory cell transistors MC are connected to word lines WL0 to WLn on a row basis. The drains of the individual memory cell transistors MC are connected to bit lines BL0 to BLm on a column basis. The sources of the individual memory cell transistors MC are all connected to a ground point Vss (source line).
FIG. 3 shows the relationship between the control gate voltage and the drain current in the memory cell transistor of FIG. 1. A state where the number of electrons accumulated in the floating gate FG is relatively large (that is, the threshold voltage Vt of the memory cell transistor is high) is defined as xe2x80x9c0xe2x80x9d data. Conversely, a state where the number of electrons accumulated in the floating gate FG is relatively small (that is, the threshold voltage Vt of the memory cell transistor is low) is defined as xe2x80x9c1xe2x80x9d data. The bias conditions for data reading, erasing, and writing are shown in TABLE 1:
The data is read by applying voltage Vd (=1 V) to the drain of the memory cell transistor, voltage Vs (=0 V) to the source, and voltage Vg (=5 V) to the control gate CG. Whether the stored data is xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d is determined, depending on whether cell current Icell flows or not.
Erasing is effected all at once on the memory cells that share the source and the P-well region 102. When the drain is set in the floating state, the source voltage Vs is set to Vs=10 V, and the control gate voltage Vg is set to Vg=xe2x88x927 V, electrons flow from the floating gate FG to the substrate because of an F-N tunnel phenomenon, which sets all of the memory cells to be erased to xe2x80x9c1xe2x80x9d data.
In contrast, writing is done bit by bit. In a state where the source voltage Vs is set to Vs=0 V and the control gate voltage Vg is set to Vg=9 V, a 5 V bias (drain voltage Vd=5 V) is applied to the bit line of the cell into which xe2x80x9c0xe2x80x9d is to be written, which causes high-energy electrons generated in a channel hot electron phenomenon to be injected into the floating gate. At this time, when the bit line to be kept at xe2x80x9c1xe2x80x9d is set to 0 V (drain voltage Vd=0 V), this prevents electrons from being injected, resulting in no change in the threshold voltage Vt.
Next, to check the program or erase operation, program verify or erase verify is performed. In the program verify, the control gate voltage Vg is set to a voltage Vpv higher than that in reading, thereby performing xe2x80x9c0xe2x80x9d reading. Then, a write operation and a program verify operation are carried out alternately. When all of the cells to be written into have the xe2x80x9c0,xe2x80x9d the writing operation is ended. Similarly, in erasing, a voltage Vev lower than the voltage in reading is applied to the control gate CG, thereby carrying out a xe2x80x9c1xe2x80x9d reading erase verify operation, which secures the cell current Icell sufficiently. As described above, the word-line voltage to the cell varies according to the operation mode.
With the recent improvements in the data processing speed of CPUs (Central Processing Units), flash memories are required to have higher-speed data transmission speed. Such flash memory as shortens the total data output time of consecutive words by having a page mode reading function as DRAM or SRAM has been put on the market (see ISSCC2001 DIGEST OF TECHNICAL PAPERS pp. 32-33, February 2001, B. Pathank et al., xe2x80x9cA 1.8-V 64-Mb 100-MHz Flexible Read While Write Flash Memoryxe2x80x9d). A collection of words, that is, a page, is specified by a page address. Any word on the page is specified by an intra-page address (in-page address). Since words on the page have consecutive addresses, the intra-page addresses are allocated to the column side. Therefore, in a case where low-order addresses are allocated to the column side, addresses higher in order than these addresses are allocated to the row side, and addresses still higher in order are allocated to block addresses, when a program composed of several tens of to hundreds of consecutive words is read, the number of word lines to be selected is smaller than that in a conventional method of allocating low-order addresses to the row side, middle-order addresses to the column side, and high-order addresses to block addresses. As a result, the time during which reading stress per line is applied becomes longer, which makes it more difficult to maintain the data reliability.
For example, when cells for 32 words are connected to a single word line, consider a case where 128 words continue to be read for ten years. When there is no page mode function, since allocating the low-order addresses to the rows makes it possible to read 128 word lines equally, the stress time per word line is 3xc3x97108 sec/128 words=3xc3x97106 sec. On the other hand, when the page size is 8 words, four pages are allocated to a single word line and 128 words are allocated to four word lines. As a result, since eight words can be read during the time required to read one word, the word line stress time with respect to the time required to read eight words is xe2x85x9. However, because the number of word lines decreases to {fraction (4/128)}, the length of time that a single word line is selected becomes 32 times the present value. As a result, the word line stress time (or read disturb time) is four times as long as that when there is no page mode.
As described above, the conventional nonvolatile semiconductor memory with a page mode reading function to realize high-speed data transfer speed has the problem of increasing the read disturb time. Measures to deal with this problem have been needed.
According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory comprising: a plurality of nonvolatile memory cells, at least one of the plurality of nonvolatile memory cells is addressed by address signals Ai (i=0, . . . , Ixe2x88x921), each of the address signals Ai (i=0, . . . , Ixe2x88x921) including first address subset Aj (j=0, . . . , Jxe2x88x921), second address subset Ak (k=J, . . . , Kxe2x88x921), and third address subset Al (l=K, . . . , Lxe2x88x921); a plurality of word lines and a plurality of bit lines which are connected to the plurality of nonvolatile memory cells; an address buffer to which the first address subset is inputted as a first column address, the second address subset is inputted as a first row address, and a third address subset is inputted as a second column address; and a decoder to which the output signal of the address buffer is supplied and which is configured to select at least one of the plurality of nonvolatile memory cells, wherein the plurality of bit lines are selected by at least the third address subset, and the plurality of word lines are selected by at least the second address subset.
According to another aspect of the present invention, there is provided a nonvolatile semiconductor memory with at least as many sense amplifiers as correspond to 2N1 words comprising: a plurality of nonvolatile memory cells; a plurality of word lines and a plurality of bit lines which are connected to the plurality of nonvolatile memory cells; an address buffer to which an N1 number of address subset of the lowest order are inputted as a first column address, an N2 number of address subset higher than any of the N1 number of address subset are inputted as a first row address, and an N3 number of address subset higher in order than any of the N2 number of address subset are inputted as a second column address; and a decoder to which the output signal of the address buffer is supplied and which is configured to select at least one of the plurality of nonvolatile memory cells, wherein the plurality of bit lines are selected by at least the second column address, and the plurality of word lines are selected by at least the first row address.
According to still another aspect of the present invention, there is provided a nonvolatile semiconductor memory with at least as many sense amplifiers as correspond to 2N1 words comprising: a plurality of nonvolatile memory cells; a plurality of word lines and a plurality of bit lines which are connected to the plurality of nonvolatile memory cells; an address buffer to which an N1 number of address subset of the lowest order are inputted as an intra-page address, an N2 number of address subset higher in order than any of the N1 number of address subset are inputted as a first row address, and an N3 number of address subset higher in order than any of the N2 number of address subset are inputted as a page address; and a decoder to which the output signal of the address buffer is supplied and which is configured to select at least one of the plurality of nonvolatile memory cells, wherein the plurality of bit lines are selected by at least the page address, and the plurality of word lines are selected by at least the first row address.
According to still another aspect of the present invention, there is provided a nonvolatile semiconductor memory comprising: a plurality of nonvolatile memory cells; a plurality of word lines and a plurality of bit lines which are connected to the plurality of nonvolatile memory cells; a first address buffer to which a first address subset is inputted; a second address buffer to which a second address subset higher in order than the first address subset is inputted; a third address buffer to which a third address subset higher in order than the second address subset is inputted; a row decoder to which the output of the second address buffer is inputted and which selects one of the plurality of word lines when reading the data stored in the plurality of nonvolatile memory cells; a column decoder to which the output of the third address buffer is inputted and which selects at least an N (where N is a positive integer equal to or larger than 2) number of bit lines from the plurality of bit lines when reading the data stored in the plurality of nonvolatile memory cells; at least an N number of sense amplifiers which read the data in the memory cells selected for reading; a multiplexer to which the output of the first address buffer is inputted and which selects an M number of outputs from the outputs of the N number of sense amplifiers; and an output buffer to which the output of the multiplexer is inputted.
According to still another aspect of the present invention, there is provided a nonvolatile semiconductor memory comprising: a plurality of nonvolatile memory blocks, each of which includes a plurality of nonvolatile memory cells, a plurality of word lines and a plurality of bit lines which are connected to the plurality of nonvolatile memory cells, a row decoder which selects one of the plurality of word lines when reading the data stored in the plurality of nonvolatile memory cells, and a column decoder which selects at least an N (where N is a positive integer equal to or larger than 2) number of bit lines from the plurality of bit lines when reading the data stored in the plurality of nonvolatile memory cells; a first address buffer to which a first address subset is inputted; a second address buffer to which a second address subset higher in order than the first address subset is inputted; a third address buffer to which a third address subset higher in order than the second address subset is inputted; a fourth address buffer to which a fourth address subset higher in order than the third address subset is inputted; at least an N number of sense amplifiers which read the data in the memory cells selected for reading; a multiplexer to which the output of the first address buffer is inputted and which selects an M number of outputs from the outputs of the N number of sense amplifiers; an output buffer to which the output of the multiplexer is inputted; and a block decoder to which the output of the fourth address buffer is inputted and which selects one of the plurality of nonvolatile memory blocks when reading the data stored in the plurality of nonvolatile memory cells, wherein one of the word-lines is selected by the output of the second address buffer and the output of the block decoder, and at least one of the bit-lines is selected by the output of at least the third address buffer and the output of the block decoder.
According to still another aspect of the present invention, there is provided a nonvolatile semiconductor memory comprising: a plurality of nonvolatile memory blocks, each of which includes a plurality of nonvolatile memory cells, a plurality of word lines and a plurality of bit lines which are connected to the plurality of nonvolatile memory cells, a row decoder which selects one of the plurality of word lines when reading the data stored in the plurality of nonvolatile memory cells, and a column decoder which selects at least an N (where N is a positive integer equal to or larger than 2) number of bit lines from the plurality of bit lines when reading the data stored in the plurality of nonvolatile memory cells; a first address buffer to which a first address subset is inputted; a second address buffer to which a second address subset higher in order than the first address subset is inputted; a third address buffer to which a third address subset higher in order than the second address subset is inputted; a fourth address buffer to which a fourth address subset higher in order than the third address subset is inputted; a fifth address buffer to which a fifth address subset higher in order than the fourth address subset is inputted; at least an N number of sense amplifiers which read the data in the memory cells selected for reading; a multiplexer to which the output of the first address buffer is inputted and which selects an M number of outputs from the outputs of the N number of sense amplifiers; an output buffer to which the output of the multiplexer is inputted; and a block decoder to which the output of the fifth address buffer is inputted and which selects one of the plurality of nonvolatile memory blocks when reading the data stored in the plurality of nonvolatile memory cells, wherein one of the word-lines is selected by the outputs of the second and fourth address buffers and the output of the block decoder, and at least one of the bit-lines is selected by the output of at least the third address buffer and the output of the block decoder.